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LT1806/lt1807 1 18067fc typical application description 325mhz, single/dual, rail-to-rail input and output, low distortion, low noise precision op amps the lt ? 1806/lt1807 are single/dual low noise rail-to-rail input and output unity-gain stable op amps that feature a 325mhz gain-bandwidth product, a 140v/s slew rate and a 85ma output current. they are optimized for low voltage, high performance signal conditioning systems. the LT1806/lt1807 have a very low distortion of C 80dbc at 5mhz, a low input referred noise voltage of 3.5nv/ hz and a maximum offset voltage of 550v that allows them to be used in high performance data acquisition systems. the LT1806/lt1807 have an input range that includes both supply rails and an output that swings within 20mv of either supply rail to maximize the signal dynamic range in low supply applications. the LT1806/lt1807 maintain their performance for supplies from 2.5v to 12.6v and are speci? ed at 3v, 5v and 5v supplies. the inputs can be driven beyond the supplies without damage or phase reversal of the output. the LT1806 is available in an 8-pin so package with the standard op amp pinout and a 6-pin tsot-23 package. the lt1807 features the standard dual op amp pinout and is available in 8-pin so and msop packages.these devices can be used as plug-in replacements for many op amps to improve input/output range and performance. features applications n low voltage, high frequency signal processing n driving a/d converters n rail-to-rail buffer ampli? ers n active filters n video line driver n gain-bandwidth product: 325mhz n slew rate: 140v/s n wide supply range: 2.5v to 12.6v n large output current: 85ma n low distortion, 5mhz: C80dbc n low voltage noise: 3.5nv/ hz n input common mode range includes both rails n output swings rail-to-rail n input offset voltage (rail-to-rail): 550v max n common mode rejection: 106db typ n power supply rejection: 105db typ n unity-gain stable n power down pin (LT1806) n operating temperature range: C 40c to 85c n single in so-8 and 6-pin low pro? le (1mm) thinsot? packages n dual in so-8 and 8-pin msop packages C + 1/2 lt1807 r2 909 r5 49.9 r6 49.9 r3 100 v in r1 100 c1 5.6pf c2 5.6pf C + 1/2 lt1807 r4 1k c3 470pf lt c ? 1420 pga gain = 1 v ref = 4.096v 12 bits 10msps +av in 5v C5v 18067 ta01 Cav in gain of 20 differential a/d driver frequency (mhz) 0 C120 amplitude (db) C100 C80 C60 C40 C20 0 1234 18067 ta02 5 v s = p 5v a v = 20 f sample = 10msps f in = 1.4086mhz sfdr = 83db nonaveraged v in = 200mv p-p 4096 point fft response l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
LT1806/lt1807 2 18067fc absolute maximum ratings total supply voltage (v + to v C ) ............................. 12.6v input voltage (note 2) .............................................. vs input current (note 2) .......................................... 10ma output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4) ...C 40c to 85c (note 1) order information lead free finish tape and reel part marking package description specified temperature range LT1806cs6#pbf LT1806cs6#trpbf ltnk 6-lead plastic tsot-23 0c to 70c LT1806is6#pbf LT1806is6#trpbf ltnl 6-lead plastic tsot-23 C40c to 85c LT1806cs8#pbf LT1806cs8#trpbf 1806 8-lead plastic so 0c to 70c LT1806is8#pbf LT1806is8#trpbf 1806i 8-lead plastic so C40c to 85c lt1807cms8#pbf lt1807cms8#trpbf lttt 8-lead plastic msop 0c to 70c lt1807ims8#pbf lt1807ims8#trpbf lttv 8-lead plastic msop C40c to 85c lt1807cs8#pbf lt1807cs8#trpbf 1807 8-lead plastic so 0c to 70c lt1807is8#pbf lt1807is8#trpbf 1807i 8-lead plastic so C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ out 1 v C 2 +in 3 6 v + 5 shdn 4 Cin top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 160c/w (note 9) top view nc v + out nc shdn Cin +in v C s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 C + t jmax = 150c, ja = 100c/w (note 9) 1 2 3 4 out a Cin a +in a v C 8 7 6 5 v + out b Cin b +in b top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 135c/w (note 9) top view v + out b Cin b +in b out a Cin a +in a v C s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 C + C + t jmax = 150c, ja = 100c/w (note 9) pin configuration speci? ed temperature range (note 5) ....C 40c to 85c junction temperature ........................................... 150c storage temperature range ..................C 65c to 150c lead temperature (soldering, 10 sec)................... 300c
LT1806/lt1807 3 18067fc electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + v cm = v C v cm = v + (LT1806 sot-23) v cm = v C (LT1806 sot-23) 100 100 100 100 550 550 700 700 v v v v v os input offset voltage shift v cm = v C to v + v cm = v C to v + (LT1806 sot-23) 50 100 550 700 v v input offset voltage match (channel-to-channel) (note 10) v cm = v C to v + 200 1000 v i b input bias current v cm = v + v cm = v C + 0.2v C13 1 C5 4a a i b input bias current shift v cm = v C to v + 617 a input bias current match (channel-to-channel) (note 10) v cm = v + v cm = v C + 0.2v 0.03 0.05 1.2 3.0 a a i os input offset current v cm = v + v cm = v C + 0.2v 0.03 0.05 0.6 1.5 a a i os input offset current shift v cm = v C + 0.2v to v + 0.08 2.1 a input noise voltage 0.1hz to 10hz 800 nv p-p e n input noise voltage density f = 10khz 3.5 nv/ hz i n input noise current density f = 10khz 1.5 pa/ hz c in input capacitance 2pf a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 75 9 60 220 22 150 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + 79 74 100 95 db db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + 73 68 100 95 db db input common mode range v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 90 105 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v 84 105 db minimum supply voltage (note 6) 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma 8 50 170 50 130 375 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma 15 85 350 65 180 650 mv mv mv t a = 25c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted.
LT1806/lt1807 4 18067fc the l denotes the speci? cations which apply over the 0c < t a < 70c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. electrical characteristics t a = 25c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units i sc short-circuit current v s = 5v v s = 3v 35 30 85 65 ma ma i s supply current per ampli? er 913 ma disable supply current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v 0.40 0.22 0.9 0.7 ma ma i shdn shdn pin current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v 150 100 350 300 a a shutdown output leakage current v shdn = 0.3v 0.1 75 a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 6mhz 325 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v 125 v/s fpbw full-power bandwidth v s = 5v, v out = 4v p-p 10 mhz hd harmonic distortion v s = 5v, a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C78 dbc t s settling time 0.01%, v s = 5v, v step = 2v, a v = 1, r l = 1k 60 ns g differential gain (ntsc) v s = 5v, a v = 2, r l = 150 0.015 % ? differential phase (ntsc) v s = 5v, a v = 2, r l = 150 0.05 deg symbol parameter conditions min typ max units v os input offset voltage v cm = v + v cm = v C v cm = v + (LT1806 sot-23) v cm = v C (LT1806 sot-23) l l l l 200 200 200 200 700 700 850 850 v v v v v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 1.5 1.5 5 5 v/c v/c v os input offset voltage shift v cm = v C to v + v cm = v C to v + (LT1806 sot-23) l l 100 100 700 850 v v input offset voltage match (channel-to-channel) (note 10) v cm = v C , v cm = v + l 300 1200 v i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C15 1 C5 5a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 620 a
LT1806/lt1807 5 18067fc electrical characteristics the l denotes the speci? cations which apply over the 0c < t a < 70c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.03 0.05 1.5 3.5 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.03 0.05 0.75 1.80 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.08 2.55 a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l l l 60 7.5 45 175 20 140 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 77 72 94 89 db db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 71 66 94 89 db db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 88 105 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 82 105 db minimum supply voltage (note 6) v cm = v o = 0.5v l 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma l l l 12 60 180 60 140 425 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma l l l 30 110 360 120 220 700 mv mv mv i sc short-circuit current v s = 5v v s = 3v l l 30 25 65 55 ma ma i s supply current per ampli? er l 10 14 ma disable supply current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 0.40 0.22 1.1 0.9 ma ma i shdn shdn pin current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 160 110 400 350 a a shutdown output leakage current v shdn = 0.3v l 1a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 6mhz l 300 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v l 100 v/s fpbw full-power bandwidth v s = 5v, v o = 4v p-p l 8 mhz
LT1806/lt1807 6 18067fc electrical characteristics the l denotes the speci? cations which apply over the C40c < t a < 85c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage v cm = v + v cm = v C v cm = v + (LT1806 sot-23) v cm = v C (LT1806 sot-23) l l l l 200 200 200 200 800 800 950 950 v v v v v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 1.5 1.5 5 5 v/c v/c v os input offset voltage shift v cm = v C to v + v cm = v C to v + (LT1806 sot-23) l l 100 100 800 950 v v input offset voltage match (channel-to-channel) (note 10) v cm = v C , v cm = v + l 200 1400 v i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C16 1 C5 6a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 622 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.02 0.05 1.8 4 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.02 0.05 0.9 2.1 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.07 3 a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l l l 50 6 35 140 16 100 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 75 71 94 89 db db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 69 65 94 89 db db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 86 105 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 80 105 db minimum supply voltage (note 6) v cm = v o = 0.5v l 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 20ma l l l 15 65 170 70 150 400 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 20ma l l l 30 110 350 130 240 700 mv mv mv i sc short-circuit current v s = 5v v s = 3v l l 22 20 45 40 ma ma i s supply current per ampli? er l 11 16 ma disable supply current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 0.4 0.3 1.2 1 ma ma
LT1806/lt1807 7 18067fc t a = 25c. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + v cm = v C v cm = v + (LT1806 sot-23) v cm = v C (LT1806 sot-23) 100 100 100 100 700 700 750 750 v v v v v os input offset voltage shift v cm = v C to v + v cm = v C to v + (LT1806 sot-23) 50 50 700 750 v v input offset voltage match (channel-to-channel) (note 10) v cm = v C , v cm = v + 200 1200 v i b input bias current v cm = v + v cm = v C + 0.2v C14 1 C5 5a a i b input bias current shift v cm = v C + 0.2v to v + 619 a input bias current match (channel-to-channel) (note 10) v cm = v + v cm = v C + 0.2v 0.03 0.05 1.4 3.2 a a i os input offset current v cm = v + v cm = v C + 0.2v 0.03 0.04 0.7 1.6 a a i os input offset current shift v cm = v C + 0.2v to v + 0.07 2.3 a input noise voltage 0.1hz to 10hz 800 nvp-p e n input noise voltage density f = 10khz 3.5 nv/ hz i n input noise current density f = 10khz 1.5 pa/ hz c in input capacitance f = 10khz 2 pf a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2.5v to 2.5v, r l = 100 100 10 300 27 v/mv v/mv electrical characteristics the l denotes the speci? cations which apply over the C40c < t a < 85c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5) symbol parameter conditions min typ max units i shdn shdn pin current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 170 120 450 400 a a shutdown output leakage current v shdn = 0.3v l 1.2 a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 6mhz l 250 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v l 80 v/s fpbw full-power bandwidth v s = 5v, v o = 4v p-p l 6 mhz
LT1806/lt1807 8 18067fc electrical characteristics t a = 25c. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. symbol parameter conditions min typ max units cmrr common mode rejection ratio v cm = v C to v + 83 106 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + 77 106 db input common mode range v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v 90 105 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v 84 105 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma 14 55 180 60 140 450 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma 20 90 360 70 200 700 mv mv mv i sc short-circuit current 40 85 ma i s supply current per ampli? er 11 16 ma disable supply current v shdn = 0.3v 0.4 1.2 ma i shdn shdn pin current v shdn = 0.3v 150 350 a shutdown output leakage current v shdn = 0.3v 0.3 75 a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 6mhz 170 325 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, measured at v o = 3v 70 140 v/s fpbw full-power bandwidth v o = 8v p-p 5.5 mhz hd harmonic distortion a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C 80 dbc t s settling time 0.01%, v step = 8v, a v = 1, r l = 1k 120 ns g differential gain (ntsc) a v = 2, r l = 150 0.01 % ? differential phase (ntsc) a v = 2, r l = 150 0.01 deg
LT1806/lt1807 9 18067fc the l denotes the speci? cations which apply over the 0c < t a < 70c temperature range. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + v cm = v C v cm = v + (LT1806 sot-23) v cm = v C (LT1806 sot-23) l l l l 200 200 200 200 800 800 900 900 v v v v v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 1.5 1.5 5 5 v/c v/c v os input offset voltage shift v cm = v C to v + v cm = v C to v + (LT1806 sot-23) l l 100 100 800 900 v v input offset voltage match (channel-to-channel) (note 10) v cm = v C , v cm = v + l 300 1400 v i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C15 1 C6 6a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 721 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.03 0.04 1.8 3.8 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.03 0.04 0.9 1.9 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.07 2.8 a a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2.5v to 2.5v, r l = 100 l l 80 8 250 25 v/mv v/mv cmrr common mode rejection ratio v cm = v C to v + l 81 100 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 75 100 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 88 105 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v l 82 106 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma l l l 18 60 185 80 160 500 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma l l l 40 110 360 140 240 750 mv mv mv i sc short-circuit current l 35 75 ma i s supply current per ampli? er l 14 20 ma disable supply current v shdn = 0.3v l 0.4 1.4 ma i shdn shdn pin current v shdn = 0.3v l 160 400 a shutdown output leakage current v shdn = 0.3v l 1a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 6mhz l 150 300 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, measure at v o = 3v l 60 120 v/s fpbw full-power bandwidth v o = 8v p-p l 4.5 mhz
LT1806/lt1807 10 18067fc electrical characteristics the l denotes the speci? cations which apply over the ? 40c < t a < 85c temperature range. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage v cm = v + v cm = v C v cm = v + (LT1806 sot-23) v cm = v C (LT1806 sot-23) l l l l 200 200 200 200 900 900 975 975 v v v v v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 1.5 1.5 5 5 v/c v/c v os input offset voltage shift v cm = v C to v + v cm = v C to v + (LT1806 sot-23) l l 100 100 900 975 v v input offset voltage match (channel-to-channel) (note 10) v cm = v C , v cm = v + l 300 1600 v i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C16 1.2 C5 7a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 623 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.03 0.04 2 4.5 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.03 0.04 1.0 2.2 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.07 3.2 a a vol large-signal voltage gain v o = C 4v to 4v, r l = 1k v o = C2v to 2v, r l =100 l l 60 7 175 17 v/mv v/mv cmrr common mode rejection ratio v cm = v C to v + l 80 100 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 74 100 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 86 105 db psrr match (channel-to-channel) (note 10) l 80 105 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 20ma l l l 20 65 200 100 170 500 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 20ma l l l 50 115 360 160 260 700 mv mv mv i sc short-circuit current l 25 55 ma i s supply current per ampli? er l 15 22 ma disable supply current v shdn = 0.3v l 0.45 1.5 ma i shdn shdn pin current v shdn = 0.3v l 170 400 a shutdown output leakage current v shdn = 0.3v l 1.2 a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns
LT1806/lt1807 11 18067fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. this parameter is guaranteed to meet speci? ed performance through design and/or characterization. it is not 100% tested. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 4: the LT1806c/LT1806i and lt1807c/lt1807i are guaranteed functional over the temperature range of C40c and 85c. note 5: the LT1806c/lt1807c are guaranteed to meet speci? ed performance from 0c to 70c. the LT1806c/lt1807c are designed, characterized and expected to meet speci? ed performance from C40c to 85c but are not tested or qa sampled at these temperatures. the LT1806i/ lt1807i are guaranteed to meet speci? ed performance from C40c to 85c. note 6: minimum supply voltage is guaranteed by power supply rejection ratio test. note 7: output voltage swings are measured between the output and power supply rails. note 8: this parameter is not 100% tested. note 9: thermal resistance varies depending upon the amount of pc board metal attached to the v C pin of the device. ja is speci? ed for a certain amount of 2oz copper metal trace connecting to the v C pin as described in the thermal resistance tables in the applications information section. note 10: matching parameters are the difference between the two ampli? ers of the lt1807. electrical characteristics the l denotes the speci? cations which apply over the ? 40c < t a < 85c temperature range. v s = 5v, v shdn = open; v cm = 0v, v out = 0v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 6mhz l 125 290 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, measure at v o = 3v l 50 100 v/s fpbw full-power bandwidth v o = 8v p-p l 4 mhz typical performance characteristics input offset voltage (v) C500 percent of units (%) 30 40 50 300 18067 g01 20 10 0 C300 C100 100 500 v s = 5v, 0v v cm = 0v input offset voltage (v) C500 percent of units (%) 30 40 50 300 18067 g02 20 10 0 C300 C100 100 500 v s = 5v, 0v v cm = 5v input offset voltage (v) C500 percent of units (%) 30 40 50 300 18067 g03 20 10 0 C300 C100 100 500 v s = 5v, 0v v os distribution, v cm = 0v (pnp stage) v os distribution, v cm = 5v (npn stage) v os shift for v cm = 0v to 5v
LT1806/lt1807 12 18067fc total supply voltage (v) 1.0 C1.0 change in offset voltage (mv) C0.8 C0.4 C0.2 0 1.0 0.4 2.0 3.0 3.5 18067 g10 C0.6 0.6 0.8 0.2 1.5 2.5 4.0 4.5 5.0 t a = 125c t a = C55c t a = 25c power supply voltage ( p v) 1.5 output short-circuit current (ma) C40 80 100 120 2.5 3.5 4.0 18067 g11 C80 40 0 C60 60 C100 20 C20 2.0 3.0 4.5 5.0 t a = C55c t a = C55c t a = 125c t a = 25c sinking sourcing t a = 125c t a = 25c shdn pin voltage (v) 0 0 supply current (ma) 2 6 8 10 2 4 5 18 18067 g12 4 13 12 14 16 t a = 125c t a = C55c t a = 25c v s = 5v, 0v minimum supply voltage output short-circuit current vs power supply voltage supply current vs shdn pin voltage typical performance characteristics total supply voltage (v) 0 supply current (ma) 12 18067 g04 345 2 1 678 91011 20 15 10 5 0 t a = 125c t a = 25c t a = C55c input common mode voltage (v) 0 offset voltage (v) 100 300 500 4 18067 g05 C100 C300 0 200 400 C200 C400 C500 1 2 3 5 t a = 125c t a = C55c t a = 25c v s = 5v, 0v typical part common mode voltage (v) C1 C10 input bias current (a) C5 0 5 0123 18067 g06 456 t a = 125c t a = 25c t a = C55c v s = 5v, 0v t a = 125c t a = 25c t a = C55c supply current per amp vs supply voltage offset voltage vs input common mode input bias current vs common mode voltage temperature (c) C50 C8 input bias (a) C7 C5 C4 C3 2 C1 C20 10 25 85 18067 g07 C6 0 1 C2 C35 C5 40 55 70 npn active v s = 5v, 0v v cm = 5v pnp active v s = 5v, 0v v cm = 0v load current (ma) 0.01 0.001 output saturation voltage (v) 0.1 10 0.1 1 10 100 18067 g08 0.01 1 v s = p 5v t a = 125c t a = 25c t a = C55c load current (ma) 0.01 0.001 output saturation voltage (v) 0.1 10 1 100 0.1 10 18067 g09 0.01 1 t a = 125c t a = C55c t a = 25c v s = p 5v input bias current vs temperature output saturation voltage vs load current (output low) output saturation voltage vs load current (output high)
LT1806/lt1807 13 18067fc typical performance characteristics shdn pin voltage (v) 0 shdn pin current (a) C60 C20 20 4 18067 g13 C100 C140 C80 C40 0 C120 C160 C180 1 2 3 5 t a = 125c t a = C55c t a = 25c v s = 5v, 0v output voltage (v) 0 C500 input voltage (v) C300 C100 100 0.5 1.0 1.5 2.0 18067 g14 2.5 300 500 C400 C200 0 200 400 3.0 r l = 1k r l = 100 v s = 3v, 0v r l to gnd output voltage (v) 0 C500 input voltage (v) C300 C100 100 0.5 1.0 1.5 2.0 18067 g15 2.5 300 500 C400 C200 0 200 400 3.0 3.5 4.0 4.5 5.0 r l = 1k r l = 100 v s = 5v, 0v r l to gnd shdn pin current vs shdn pin voltage open-loop gain open-loop gain output voltage (v) C5 C500 input voltage (v) C300 C100 100 C4 C3 C2 C1 18067 g16 0 300 500 C400 C200 0 200 400 12345 r l = 1k r l = 100 v s = p 5v output current (ma) C100 C2.5 offset voltage (mv) C1.5 C0.5 0.5 C80 C60 C40 C20 18067 g17 0 1.5 2.5 C2.0 C1.0 0 1.0 2.0 20 40 60 80 100 t a = 125c t a = C55c t a = 25c v s = p 5v time after power-up (sec) 0 offset voltage drift (v) 25 30 35 160 140 120 100 80 18067 g18 20 15 0 20 40 60 10 5 45 40 v s = p 5v v s = p 2.5v v s = p 1.5v open-loop gain offset voltage vs output current warm-up drift vs time (LT1806s8) frequency (khz) 0.1 0 8 10 12 1 10 100 18067 g19 6 4 2 noise voltage (nv/ ? hz) v s = 5v, 0v npn active v cm = 4.5v pnp active v cm = 2.5v frequency (khz) 0.1 0 8 10 12 1 10 100 18067 g19 6 4 2 noise current (pa/ ? hz) v s = 5v, 0v npn active v cm = 4.5v pnp active v cm = 2.5v time (sec) 0 output voltage (nv) 200 600 1000 8 18067 g21 C200 C600 0 400 800 C400 C800 C1000 2 1 4 3 67 9 5 10 input noise voltage vs frequency input noise current vs frequency 0.1hz to 10hz output voltage noise
LT1806/lt1807 14 18067fc frequency (hz) 100k 0.001 output impedance () 0.01 0.1 1 10 100 600 1m 10m 100m 500m 18067 g28 v s = 5v, 0v a v = 10 a v = 2 a v = 1 frequency (mhz) 0.01 40 common mode rejection ratio (db) 50 60 70 80 0.1 1 10 100 500 18067 g29 30 20 10 0 90 100 v s = 5v, 0v frequency (mhz) 0.001 40 power supply rejection ratio (db) 50 60 70 80 0.01 0.1 1 10 100 18067 g30 30 20 10 0 90 100 v s = 5v, 0v t a = 25c negative supply positive supply output impedance vs frequency common mode rejection ratio vs frequency power supply rejection ratio vs frequency typical performance characteristics total supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 8 18067 g22 400 300 350 250 200 35 45 55 30 40 50 2 1 4 3 67 9 5 10 t a = 25c phase margin gain bandwidth product temperature (c) C55 gain bandwidth (mhz) phase margin (deg) 105 18067 g23 400 300 350 250 200 35 45 55 30 40 50 C15 C35 25 5 65 85 125 45 phase margin v s = p 5v phase margin v s = 3v gbw product v s = p 5v gbw product v s = 3v temperature (c) C55 75 slew rate (v/s) 100 125 150 175 C35 C15 5 25 18067 g24 45 65 85 105 125 a v = C1 r f = r g = 1k r l = 1k v s = p 5v v s = p 2.5v gain bandwidth and phase margin vs supply voltage gain bandwidth and phase margin vs temperature slew rate vs temperature frequency (mhz) 20 gain (db) phase (deg) 40 50 70 0.1 10 100 500 18067 g25 0 1 60 30 10 C10 C20 C30 C45 45 90 180 225 C135 135 0 C90 C180 C225 phase v s = p 5v gain v s = p 5v gain v s = 3v phase v s = 3v c l = 5pf r l = 100 frequency (mhz) 0 gain (db) 12 18 30 0.1 10 100 500 18067 g26 C12 1 24 6 C6 C18 C24 C36 c l = 10pf r l = 100 v s = 3v v s = p 5v frequency (mhz) 6 gain (db) 12 15 21 0.1 10 100 500 18067 g27 0 1 18 9 3 C3 C6 C9 c l = 10pf r l = 100 v s = p 5v v s = 3v gain and phase vs frequency gain vs frequency (a v = 1) gain vs frequency (a v = 2)
LT1806/lt1807 15 18067fc typical performance characteristics capacitive load (pf) 10 0 overshoot (%) 10 20 30 40 100 1000 18067 g31 50 5 15 25 35 45 v s = 5v, 0v a v = 1 r os = 10 r os = 20 r os = r l = 50 capacitive load (pf) 10 0 overshoot (%) 10 20 30 40 100 1000 18067 g32 50 5 15 25 35 45 v s = 5v, 0v a v = 2 r os = 10 r os = 20 r os = r l = 50 20ns/div output settling resolution (2mv/div) input signal generation (2v/div) 18067 g33 v s = p 5v v out = p 4v rl = 500 t s = 120ns (settling time) series output resistor vs capacitive load series output resistor vs capacitive load 0.01% settling time frequency (mhz) 0.3 C70 distortion (dbc) C60 C50 C40 11030 18067 g34 C80 C90 C100 C110 a v = 1 v out = 2v p-p v s = p 5v r l = 100, 2nd r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.3 C70 distortion (dbc) C60 C50 C40 11030 18067 g35 C80 C90 C100 C110 a v = 1 v out = 2v p-p v s = 5v, 0v r l = 100, 2nd r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.3 C70 distortion (dbc) C60 C50 C40 11030 18067 g36 C80 C90 C100 C120 C110 a v = 2 v out = 2v p-p v s = p 5v r l = 100, 2nd r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd distortion vs frequency distortion vs frequency distortion vs frequency frequency (mhz) 0.3 C70 distortion (dbc) C60 C50 C40 11030 18067 g37 C80 C90 C100 C120 C110 a v = 2 v out = 2v p-p v s = 5v, 0v r l = 100, 2nd r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.1 4.3 output voltage swing (v p-p ) 4.4 4.5 4.6 1 10 100 18067 g38 4.2 4.1 4.0 3.9 v s = 5v, 0v a v = C1 a v = 2 distortion vs frequency maximum undistorted output signal vs frequency
LT1806/lt1807 16 18067fc typical performance characteristics 40ns/div 0v 18067 g39 v s = p 5v freq = 1.92mhz a v = 1 r l = 1k 5v large-signal response 20ns/div 18067 g40 0v v s = p 5v freq = 4.48mhz a v = 1 r l = 1k 5v small-signal response 20ns/div 18067 g41 0.5v v s = 5v, 0v freq = 5.29mhz a v = 1 r l = 1k 5v large-signal response 10ns/div 18067 g42 0v v s = 5v, 0v a v = 1 r l = 1k 5v small-signal response 100ns/div 0v 0v v in 1v/div 18067 g43 v s = 5v, 0v a v = 2 r l = 1k v out 2v/div output overdriven recovery 20ns/div 18067 g44 0v 0v v shdn 2v/div v s = 5v, 0v a v = 2 r l = 100 v out 2v/div shutdown response
LT1806/lt1807 17 18067fc rail-to-rail characteristics the LT1806/lt1807 have input and output signal range that covers from negative power supply to positive power sup- ply. figure 1 depicts a simpli? ed schematic of the ampli? er. the input stage is comprised of two differential ampli? ers, a pnp stage q1/q2 and a npn stage q3/q4 that are active over different ranges of common mode input voltage. the pnp differential pair is active between the negative supply to approximately 1.5v below the positive supply. as the input voltage moves closer toward the positive supply, the transistor q5 will steer the tail current i 1 to the current mirror q6/q7, activating the npn differential pair. the pnp pair becomes inactive for the rest of the input common mode range up to the positive supply. applications information a pair of complementary common emitter stages q14/q15 that enable the output to swing from rail to rail constructs the output stage. the capacitors c1 and c2 form the local feedback loops that lower the output impedance at high frequency. these devices are fabricated on linear technologys proprietary high speed complementary bipolar process. power dissipation the LT1806/lt1807 ampli? ers combine high speed with large output current in a small package, so there is a need to ensure that the dies junction temperature does not exceed 150c. the LT1806 is housed in an so-8 package or a 6-lead sot-23 package and the lt1807 is in an so-8 q4 q6 q3 q7 q10 q1 q13 q15 out q2 q11 q12 q9 q5 v bias i 1 d2 d1 d5 d4 d3 d6 d7 d8 esdd2 esdd1 +in Cin v C esdd3 esdd4 v + v + v C q8 r2 r1 r3 r4 r5 q14 18067 f01 + i 2 c2 c c v C + c1 buffer and output bias q17 q16 esdd5 shdn v + v C r7 100k r6 40k d9 v + v C esdd6 bias generation figure 1. LT1806 simpli? ed schematic diagram
LT1806/lt1807 18 18067fc or 8-lead msop package. all packages have the v C sup- ply pin fused to the lead frame to enhance the thermal conductance when connecting to a ground plane or a large metal trace. metal trace and plated through-holes can be used to spread the heat generated by the device to the backside of the pc board. for example, on a 3/32" fr-4 board with 2oz copper, a total of 660 square mil- limeters connects to pin 4 of lt1807 in an so-8 package (330 square millimeters on each side of the pc board) will bring the thermal resistance, ja , to about 85c/w. without extra metal trace beside the power line connecting to the v C pin to provide a heat sink, the thermal resistance will be around 105c/w. more information on thermal resistance for all packages with various metal areas connecting to the v C pin is provided in tables 1, 2 and 3. table 1. LT1806 6-lead sot-23 package copper area board area (mm 2 ) thermal resistance (junction-to-ambient) topside (mm 2 ) 270 2500 135c/w 100 2500 145c/w 20 2500 160c/w 0 2500 200c/w device is mounted on topside. table 2. LT1806/lt1807 so-8 package copper area board area (mm 2 ) thermal resistance (junction-to-ambient) topside (mm 2 ) backside (mm 2 ) 1100 1100 2500 65c/w 330 330 2500 85c/w 35 35 2500 95c/w 35 0 2500 100c/w 0 0 2500 105c/w device is mounted on topside. applications information table 3. lt1807 8-lead msop package copper area board area (mm 2 ) thermal resistance (junction-to-ambient) topside (mm 2 ) backside (mm 2 ) 540 540 2500 110c/w 100 100 2500 120c/w 100 0 2500 130c/w 30 0 2500 135c/w 0 0 2500 140c/w device is mounted on topside. junction temperature t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? ja ) the power dissipation in the ic is the function of the supply voltage, output voltage and the load resistance. for a given supply voltage, the worst-case power dissipation p d(max) occurs at the maximum quiescent supply current and at the output voltage which is half of either supply voltage (or the maximum swing if it is less than 1/2 the supply voltage). p d(max) is given by: p d(max) = (v s ? i s(max) ) + (v s /2)2/r l example: an lt1807 in so-8 mounted on a 2500mm 2 area of pc board without any extra heat spreading plane connected to its v C pin has a thermal resistance of 105c/w, ja . operating on 5v supplies with both ampli- ? ers simultaneously driving 50 loads, the worst-case power dissipation is given by: p d(max) = 2 ? (10 ? 14ma) + 2 ? (2.5) 2 /50 = 0.28 + 0.25 = 0.53w
LT1806/lt1807 19 18067fc applications information the maximum ambient temperature that the part is allowed to operate is: t a = t j C (p d(max) ? 105c/w) = 150c C (0.53w ? 105c/w) = 94c to operate the device at higher ambient temperature, connect more metal area to the v C pin to reduce the thermal resistance of the package as indicated in table 2. input offset voltage the offset voltage will change depending upon which input stage is active and the maximum offset voltage is guaranteed to less than 550v. to maintain the precision characteristics of the ampli? er, the change of v os over the entire input common mode range (cmrr) is limited to be less than 550v on a single 5v and 3v supply. input bias current the input bias current polarity depends on a given input common voltage at which the input stage is operating. when the pnp input stage is active, the input bias currents ? ow out of the input pins. when the npn input stage is activated, the input bias current ? ows into the input pins. because the input offset current is less than the input bias current, matching the source resistances at the input pins will reduce total offset error. output the LT1806/lt1807 can deliver a large output current, so the short-circuit current limit is set around 85ma to prevent damage to the device. attention must be paid to keep the junction temperature of the ic below the absolute maximum rating of 150c (refer to the power dissipation section) when the output is continuously short circuited. the output of the ampli? er has reverse-biased diodes connected to each supply. if the output is forced beyond either supply, unlimited current will ? ow through these diodes. if the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. overdrive protection when the input voltage exceeds the power supplies, two pairs of crossing diodes d1 to d4 will prevent the output from reversing polarity. if the input voltage exceeds either power supply by 700mv, diode d1/d2 or d3/d4 will turn on to keep the output at the proper polarity. for the phase reversal protection to perform properly, the input current must be limited to less than 5ma. if the ampli? er is severely overdriven, an external resistor should be used to limit the overdrive current.
LT1806/lt1807 20 18067fc applications information the LT1806/lt1807s input stages are also protected against large differential input voltages of 1.4v or higher by a pair of back-to-back diodes, d5/d8, that prevent the emitter-base breakdown of the input transistors. the current in these diodes should be limited to less than 10ma when they are active. the worst-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity gain con? guration. in addition, the ampli? er is protected against esd strikes up to 3kv on all pins by a pair of protection diodes, esdd1 to esdd6, on each pin that are connected to the power supplies as shown in figure 1. capacitive load the LT1806/lt1807 are optimized for high bandwidth and low distortion applications. they can drive a capacitive load of about 20pf in a unity-gain con? guration, and more for higher gain. when driving a larger capacitive load, a resistor of 10 to 50 should be connected between the output and the capacitive load to avoid ringing or oscilla- tion. the feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. graphs on capacitive loads indicate the transient response of the ampli? er when driving the capacitive load with a speci? ed series resistor. feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. for instance, the LT1806/lt1807 in a noninverting gain of 2, set up with two 1k resistors and a capacitance of 3pf (part plus pc board) will probably ring in transient response. the pole is formed at 106mhz that will reduce phase margin by 34 degrees when the crossover frequency of the ampli? er is around 70mhz. a capacitor of 3pf or higher connected across the feedback resistor will eliminate any ringing or oscillation. shdn pin the LT1806 has a shdn pin to reduce the supply current to less than 0.9ma. when the shdn pin is pulled low, it will generate a signal to power down the device. if the pin is left unconnected, an internal pull-up resistor of 40k will keep the part fully operating as shown in figure 1. the output will be high impedance during shutdown, and the turn-on and turn-off time is less than 100ns. because the input is protected by a pair of back-to-back diodes, the input signal will feed through to the output during shutdown mode if the amplitude of signal between the inputs is larger than 1.4v.
LT1806/lt1807 21 18067fc typical applications driving a/d converter the LT1806/lt1807 have 60ns settling time to 0.01% on a 2v step signal, and 20 output impedance at 100mhz, that makes them ideal for driving high speed a/d convert- ers. with the rail-to-rail input and output, and low supply voltage operation, the LT1806/lt1807 are also desirable for single supply applications. as shown in the application on the front page of this data sheet, the lt1807 drives a 10msps, 12-bit, ltc1420 adc in a gain of 20. driving the ltc1420 differentially will optimize the signal-to-noise ratio, snr, and the total harmonic distortion, thd, of the a/d converter. the lowpass ? lter, r5, r6 and c3 reduce noise or distortion products that might come from the input signal. high quality capacitors and resistors, npo chip capacitor and metal ? lm surface mount resistors, should be used since these components can add to distortion. the voltage glitch of the converter, due to its sampling nature is buffered by the lt1807, and the ability of the ampli? er to settle it quickly will affect the spurious free dynamic range of the system. figure 2 depicts the LT1806 driving ltc1420 at noninverting gain of 2 con? guration. the fft responses show a better than 92db of spurious free dynamic range, sfdr. figure 2. noninverting a/d driver C + LT1806 ltc1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps C5v C5v ? ? ? r2 1k r1 1k v in 1.5v p-p c1 470pf Ca in 18067 f02 +a in r3 49.9 figure 3. 4096 point fft response frequency (mhz) 0 C120 amplitude (db) C100 C80 C60 C40 C20 0 1234 18067 f03 5 v s = p 5v a v = 2 f sample = 10msps f in = 1.4086mhz sfdr = 92.5db
LT1806/lt1807 22 18067fc typical applications single supply video line driver the LT1806/lt1807 are wideband rail-to-rail op amps with large output current that allows them to drive video signals in low supply applications. figure 4 depicts a single supply video line driver with ac coupling to minimize the quies- cent power dissipation. resistors r1 and r2 are used to level-shift the input and output to provide the largest signal swing. the gain of 2 is set up with r3 and r4 to restore the signal at v out , which is attenuated by 6db due to the matching of the 75 line with the back-terminated resistor, r5. the back termination will eliminate any re? ection of the signal that comes from the load. the input termination resistor, r t , is optionalit is used only if matching of the incoming line is necessary. the values of c1, c2 and c3 are selected to minimize the droop of the luminance signal. in some less stringent requirements, the value of capacitors could be reduced. the C3db bandwidth of the driver is about 90mhz on 5v supply, and the amount of peaking will vary upon the value of capacitor c4. figure 4. 5v single supply video line driver C + LT1806 v in 18067 f04 c1 33f c2 150f r t 75 r load 75 v out r2 5k r3 1k r4 1k c4 3pf r1 5k 5v 2 3 6 7 4 r5 75 75w coax cable c3 1000f + + + figure 5. video line driver frequency response frequency (mhz) C2 voltage gain (db) 4 5 C3 C4 3 0 2 1 C1 0.2 10 100 18067 f05 C5 1 v s = 5v, 0v
LT1806/lt1807 23 18067fc typical applications single 3v supply, 4mhz, 4th order butterworth filter bene? ting from a low voltage supply operation, low distortion and rail-to-rail output of LT1806/lt1807, a low distortion ? lter that is suitable for antialiasing can be built as shown in figure 6. on a 3v supply, the ? lter built with lt1807 has a passband of 4mhz with 2.5v p-p signal and stopband that is greater than 70db to frequency of 100mhz. as an option to minimize the dc offset voltage at the output, connect a series resistor of 365 and a bypass capacitor at the noninverting inputs of the ampli? ers as shown in figure 6. figure 6. single 3v supply, 4mhz, 4th order butterworth filter + C v s 2 47pf 1/2 lt1807 220pf 665 v in v out 18067 f06 365 (optional) 232 232 4.7f (optional) + C 22pf 470pf 562 274 274 1/2 lt1807 figure 7. filter frequency response frequency (hz) 10k 100k 1m 10m 100m gain (db) 18067 f07 10 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 v s = 3v, 0v v in = 2.5v p-p
LT1806/lt1807 24 18067fc typical applications 1mhz series resonant crystal oscillator with square and sinusoid outputs figure 8 shows a classic 1mhz series resonant crystal oscillator. at series resonance, the crystal is a low imped- ance and the positive feedback connection is what brings about oscillation at the series resonance frequency. the rc feedback around the other path ensures that the circuit does not ? nd a stable dc operating point and refuse to oscillate. the comparator output is a 1mhz square wave with a measured jitter of 28ps rms with a 5v supply and 40ps rms with a 3v supply. on the other side of the crystal, however, is an excellent looking sine wave except for the fact of the small high frequency glitch caused by the fast edge and the crystal capacitance (middle trace of figure 9). sinusoid amplitude stability is maintained by the fact that the sine wave is basically a ? ltered version of the square wave; the usual amplitude control loops associated with sinusoidal oscillators are not immediately necessary. 1 one can make use of this sine wave by buffering and ? ltering it, and this is the combined task of the LT1806. it is con? gured as a bandpass ? lter with a q of 5 and does a good job of cleaning up and buffering the sine wave. distortion was measured at C70dbc and C60dbc on the second and third harmonics. figure 8. lt1713 comparator is con? gured as a series resonant crystal oscillator. the LT1806 op amp is con? gured in a q = 5 bandpass filter with f c = 1mhz C + 8 square wave v s v s v s 1 7 4 5 r3 1k r4 210 r1 1k r8 2k r9 2k r5 6.49k 1k r7 15.8k r2 1k 1mhz at-cut c1 0.1f 6 3 2 c2 0.1f c4 100pf c3 100pf lt1713 C + v s 7 6 1 (nc) 4 18067 f08 v s = 2.7v to 6v 3 2 LT1806 le r6 162 100pf sine wave 200ns/div 1v/div 1v/div 3v/div 18067 f09 1 amplitude will be a linear function of comparator output swing, which is supply dependent and therefore controllable. the important difference here is that any added amplitude stabilization loop will not be faced with the classical task of avoiding regions of nonoscillation versus clipping. figure 9. oscillator waveforms with v s = 3v. top trace is comparator output. middle trace is crystal feedback to pin 2 at lt1713. bottom trace is buffered, inverted and bandpass filtered with a q of 5 by the LT1806
LT1806/lt1807 25 18067fc package description 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 6 plcs (note 3) datum a 0.09 C 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636)
LT1806/lt1807 26 18067fc msop (ms8) 0307 rev f 0.53 p 0.152 (.021 p .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 p 0.0508 (.004 p .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 o C 6 o typ detail a detail a gauge plane 12 3 4 4.90 p 0.152 (.193 p .006) 8 7 6 5 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
LT1806/lt1807 27 18067fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 o 0 o C 8 o typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 p .005 recommended solder pad layout .045 p .005 .050 bsc .030 p .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
LT1806/lt1807 28 18067fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2000 lt 0809 rev c ? printed in usa related parts part number description comments lt1395 400mhz current feedback ampli? er 800v/s slew rate, shutdown lt1399 triple 300mhz current feedback ampli? er 0.1db gain flatness to 150mhz, shutdown lt1632/lt1633 dual/quad 45mhz, 45v/s rail-to-rail input and output ampli? ers high dc accuracy 1.35mv v os(max) , 70ma output current, max supply current 5.2ma/amp lt1809/lt1810 single/dual 180mhz input and output rail-to-rail ampli? ers 350v/s slew rate, shutdown, low distortion C90dbc at 5 mhz lt1812/lt1813 3ma, 100mhz, 750v/s op amp high slew rate lt1818/lt1819 9ma, 400mhz, 2500v/s op amp ultrahigh slew rate lt6200/lt6201 165mhz rail-to-rail input and output, 0.95nv/ hz low noise op amp lowest noise lt6202/lt6203 100mhz rail-to-rail input and output, 1.9nv/ hz op amp i cc = 2.5ma typical application fet input, fast, high gain photodiode ampli? er figure 10 shows a fast, high gain transimpedance ampli? er applied to a photodiode. a jfet buffer is used for its extremely low input bias current and high speed. the lt1097 and 2n3904 keep the jfet biased at i dss for zero offset and lowest voltage noise. the jfet then drives the LT1806, with r f closing the high speed loop back to the jfet input and setting the transimpedance gain. c4 helps improve the phase margin of the fast loop. output voltage noise density was measured as 9nv/ hz with r f short circuited. with r f varied from 100k to 1m, total output noise was below 1mv rms measured over a 10mhz bandwidth. table 4 shows results achieved with various values of r f and figure 11 shows the time domain response with r f = 499k. table 4. results achieved for various r f , 1.2v output step r f 10% to 90% rise time C3db bandwidth 100k 64ns 6.8mhz 200k 94ns 4.6mhz 499k 154ns 3mhz 1m 263ns 1.8mhz figure 10. fast, high gain photodiode ampli? er C + r3 10k r1 10m siemens/ infineon sfh213fa photodiode r2 1m r f 49.9 50w 18067 f10 r5 33 r4 2.4k 3 6 4 7 v s + v s C v s C 2 c2 2200pf c3 0.1f c1 100pf c4 3pf lt1097 C + 2 6 4 7 v out * 2n5486 v s + v s + v s C v s C 3 LT1806 2n3904 *adjust parasitic capacitance at r f for desired response characteristics v s = p 5v figure 11. step response with r f = 499k 20ns/div 100mv/div 18067 f11

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